1. Field of the Invention
The present invention relates to a semiconductor device provided with a protection circuit for preventing electrostatic breakdown, specifically to the protection circuit for preventing electrostatic breakdown.
2. Description of the Related Art
Many semiconductor integrated circuit devices (hereunder, referred to structure as Metal, Oxide film, and Semiconductor, namely, the MOS structure. The MOS filed effect transistor (MOSFET) adopting the MOS structure uses a silicon oxide film (also referred to as the gate oxide film) in the insulating film to separate the gate and the channel.
When a semiconductor device is connected to, for example, an external circuit, there is an apprehension that a circuit inside the semiconductor device is subject to an electrostatic charged with the external circuit to fall into an electrostatic breakdown. In order to prevent the electrostatic breakdown, the input terminal or output terminal of the semiconductor device is provided with a protection circuit for preventing the electrostatic breakdown (hereunder, referred to as electrostatic breakdown preventing protection circuit).
The conventional electrostatic breakdown preventing protection circuit provided at the input terminal or output terminal of the semiconductor device generally uses N-type transistors. Here, the N-type transistors each are located between the input terminal and a power supply terminal, and between the input terminal and a grounding terminal. When a positive voltage is applied to the input terminal as an electrostatic, by the breakdown of the N-type transistors each, and when a negative voltage is applied as an electrostatic, by the N-type transistors each being brought into a conductive state, namely, being turned ON, the electrostatic is discharged to the power supply terminal or the grounding terminal (refer to the patent document 1).
Some protection circuits are provided with the input circuit using complementary MOSFETs (hereunder, referred to as CMOS). A conventional example of the input circuit using the CMOS will be explained with reference to FIG. 7 through FIG. 9.
FIG. 7 illustrates a conventional electrostatic breakdown preventing protection circuit. An input terminal 221 is electrically connected to an input circuit 229 being a protective object, by way of an input line 211 furnished with an input protection resistor 227. Here, an inverter is used as the input circuit 229. A power supply line 213 is connected to a power supply terminal 223, and a grounding line 215 is connected to a grounding terminal 225. Between the input line 211 and the power supply line 213 is located a P-type MOSFET (hereunder, referred to as PMOS) 251; and between the input line 211 and the grounding line 215 is located an N-type MOSFET (hereunder, referred to as NMOS) 261. Here, it is assumed that with regard to the NMOS 261, N-type source and drain are formed on a P-type substrate, and with regard to the PMOS 251, an N-type well is formed on the P-type substrate, and P-type source and drain are formed on the N-type well.
A source electrode 253, a gate electrode 257, and a well electrode 259 of the PMOS 251 are connected to the power supply line 213. A drain electrode 255 of the PMOS 251 is connected to the input line 211.
A source electrode 263, a gate electrode 267, and a substrate electrode 269 of the NMOS 261 are connected to the grounding line 215. A drain electrode 265 of the NMOS 261 is connected to the input line 211.
FIG. 8 is a circuit diagram for explaining a measuring circuit of the current vs. voltage characteristic of the NMOS 261. An output terminal of a variable voltage supply 271 is connected to the drain electrode 265 of the NMOS 261 through an ammeter 281. A grounding terminal of the variable voltage supply 271 is connected to the source electrode 263, the gate electrode 267, and the substrate electrode 269 of the NMOS 261, and also to the grounding terminal 225. A voltmeter 283 is connected to measure a voltage across the source electrode 263-drain electrode 265. Hereunder, the current measured by the ammeter 281 is referred to as a drain current ID, and the voltage measured by the voltmeter 283 is referred to as a drain voltage VD.
FIG. 9 typically illustrates a relation between the drain voltage VD and the drain current ID, by the circuit explained with reference to FIG. 8. The horizontal axis represents the drain voltage VD, and the vertical axis represents the drain current ID.
The output voltage of the variable voltage supply 271, namely, the drain voltage VD increases from the state of 0 Volt. Since the source electrode 263, gate electrode 267, and substrate electrode 269 of the NMOS 261 are grounded, and a potential difference is not given across the gate-source, the NMOS 261 is always OFF. As the drain voltage VD increases, a reverse voltage is applied to a diode formed across the drain-silicon substrate, and the drain current ID does not flow. However, as the drain voltage VD increases further to exceed a breakdown voltage VBD of the PN junction existing across the drain-silicon substrate, a current starts flowing from the drain to the substrate. This current is divided into a breakdown current flowing through the diode and a base current flowing into the emitter-base of a parasitic bipolar transistor existing in the NMOS 261. As the drain voltage VD increases further more, the breakdown current and the base current increase. At the time when the base current increases and the potential of the substrate rises higher by a forward voltage VF (about 0.6 V in case of the silicon semiconductor) of the PN junction than the potential of the source, a forward current flows into the substrate-source, accordingly the parasitic bipolar transistor of the NMOS 261 is turned ON. The drain voltage at this moment is referred to as a turn-on voltage VTO.
As the parasitic bipolar transistor is turned ON, a through current flows into the collector-emitter of the bipolar transistor, namely, into the drain-source of the NMOS 261; accordingly, the drain voltage sharply falls. To utilize this behavior of the parasitic bipolar transistor for protecting the device against the electrostatic is the main current of the protection circuit design at the present time.
Since the gate electrode and the source electrode of the NMOS 261 are on the same potential, when the parasitic bipolar transistor is turned ON, the turn-on voltage VTO is applied across the drain-gate, namely, to the gate oxide film. Generally, the turn-on voltage VTO of the parasitic bipolar transistor is set lower than a gate oxide film breakdown voltage VC.
[Patent Document 1] JPA-No.Hei9-284119 (paragraph 0007˜0013)